Design Verification Lead

📋 Description

• Define scalable verification architectures spanning IP, subsystem, and full-chip levels for
• Architect reusable, modular verification platforms supporting multiple silicon programs.
• Establish verification reuse and portable stimulus-based flows (PSS) and cross-level stimulus reuse.
• Lead high-performance, coverage-driven testbenches using UVM.
• Develop multi-level verification strategies across blocks, subsystems, and SoCs.
• Define quality metrics, coverage targets, closure strategies, and sign-off criteria.

🎯 Requirements

• Bachelor’s or Master’s in Electrical/Computer Engineering or related field.
• 10+ years in Design Verification, with experience in large-scale SoCs.
• Proven experience defining and deploying verification architectures for complex designs.
• Strong SystemVerilog and UVM skills.
• Deep knowledge of coverage-driven verification and code/functional coverage.
• SystemVerilog Assertions (SVA) and Portable Stimulus (PSS).

🎁 Benefits

• Remote-friendly working model within India.
• Opportunity to work on advanced semiconductor tech for AI/HPC.
• High technical ownership and influence over verification architecture.
• Reusable verification platforms across multiple silicon programs.
• Exposure to AI-driven verification and intelligent testing techniques.
• Collaborative environment with global teams and fast-paced execution.