Senior FPGA Engineer, Networking & Security

📋 Description

• Hybrid role; on-site in San Jose, CA three days/week.
• Design network fabric and security architecture for spacecraft HPC.
• Define concepts, write RTL, collaborate with Staff Architect and payload engineers.
• Develop onboard networking, cryptography, and security features across the system.
• Interplay between NoC, Ethernet switching/routing, and FPGA data paths.
• Publish white papers and contribute to architectural documents.

🎯 Requirements

• Bachelor’s or Master’s in CS/CE/EE or related field; 5+ years FPGA engineering, with
• Deep experience with Ethernet, link aggregation, and signal integrity at high DAC rates.
• Hands-on cryptography in hardware/firmware: AES, AES-GCM, ECC, IPSec/VPN; PQC familiarity.
• Knowledge of FEC schemes (Reed-Solomon) and translating BER/link-budget to implementations.
• Proven ability to define network packet flows, VPN termination, filtering in embedded/FPGA.
• Strong HDL/RTL skills (SystemVerilog/Verilog/VHDL) and FPGA verification.

🎁 Benefits

• Equity, medical/dental/vision insurance, 401k, disability, life insurance.
• Paid vacation, holidays, sick time, and parental leave.