Senior DFT Engineer

📋 Description

• Ownership of DFT implementation and verification for advanced SoC/ASICs
• Work on scan architectures, ATPG, memory test, boundary scan, IJTAG
• Collaborate with RTL, verification, physical design, and test teams
• DFT timing analysis, constraints, and timing closure collaboration
• Pre-silicon, gate-level simulation, and related validation activities
• Support silicon bring-up, ATE pattern validation, and post-silicon debugging

🎯 Requirements

• Bachelor’s or Master’s in Electronics/Electrical Engineering or related
• 4–7 years hands-on DFT experience in SoC/ASIC environments
• DFT methodologies: ATPG, scan compression, MBIST/LBIST, BSCAN, JTAG, IJTAG
• Experience with insertion, ATPG, pattern-generation, verification, simulation tools
• Silicon bring-up, ATE pattern validation, post-silicon debugging
• DFT verification and gate-level simulation workflows

🎁 Benefits

• Competitive compensation aligned with experience
• Fully remote work option within India
• Opportunity to work on AI/high-performance computing infrastructure
• Significant ownership and exposure to complex SoC/ASIC challenges
• Global collaboration with semiconductor professionals
• Chance to contribute to real silicon products