Sr. Design for Test (DFT) Engineer

📋 Description Perform DFT insertion on ASICs: internal scan, boundary scan, memory BIST Generate automatic and targeted test patterns Interface with Physical Design and Front End (RTL) Design Perform post-silicon DFT bring-up and test program debug Interface with ATE engineers for test program bring-up and debug Scripting and automation of DFT and ATPG flow 🎯 Requirements Bachelor's degree in Electrical Engineering (or other related fields) Minimum 13 years of industry DFT experience on ASIC designs Must have completed at least 2 tapeouts Minimum of 2 years of experience with standard DFT CAD tools and flows Hands-on experience in Python, TCL or other scripting environments DFT/post-silicon/ATPG with experience in both ASIC and semi-custom COT flow 🎁 Benefits Comprehensive Health Care Plan (Medical, Dental & Vision) Retirement Savings Matching Program Life Insurance (Basic, Voluntary & AD&D) Generous Time Off (Vacation, Sick & Public Holidays) Paid Family Leave Flexible, hybrid workplace model