ASIC Physical Design Lead

📋 Description

• Lead end-to-end ASIC physical design from RTL handoff to tapeout.
• Define implementation strategies, schedules, and quality standards.
• Develop floorplans for large SoCs incl. power/clock planning.
• Lead place-and-route using Cadence and/or Synopsys toolchains.
• Drive timing closure across corners and voltage domains.
• Oversee CTS and clock-related optimization.

🎯 Requirements

• Bachelor’s/Master’s/PhD in Electrical/Computer Engineering or related field; advanced degree
• 8+ years in ASIC Physical Design with multiple tapeouts.
• Experience at 16nm–3nm nodes.
• Deep expertise in floorplanning, PnR, CTS, STA, timing, and sign-off.
• Cadence and/or Synopsys PD toolchains proficiency.
• UPF/CPF low-power methodologies.

🎁 Benefits

• Competitive salary.
• Equity participation through ISO.
• Employer-paid medical insurance; HSA with employer contributions.
• 401(k) with employer matching.
• Flexible remote options across the United States.
• Flexible time off.