Palo AltoFull TimeEngineering
Remotely
pythonrtl designdspasicvhdlverilogsystemverilog
Job Description
📋 Description
- Join SpaceX to design and verify next-generation silicon for Starlink and related programs.
- Engage in ASIC/FPGA design and verification across RF/Analog IC, RTL, and physical design.
- Collaborate across design, verification, lab bring-up, and embedded software (C/C++ and Python).
- Contribute in all phases of design flows and silicon tapeouts for advanced nodes.
🎯 Requirements
- Graduating with a bachelor’s, master’s, or PhD in 2026 or 2027.
- Bachelor’s in engineering, mathematics, or physics.
- Experience with ASIC/SOC/FPGA/RFIC/MMIC.
🎁 Benefits
- Competitive compensation with multiple level ranges based on experience.
- Stock, bonuses, and long-term incentives where applicable.
- Comprehensive medical, vision, and dental coverage.
- 401(k) with company contributions, disability and life insurance.
- Paid parental leave, vacation, holidays, and sick leave as per policy.
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