New Graduate Engineer, Silicon Engineering

📋 Description

• Entry-level engineer for SpaceX silicon program across RF/Analog IC, RTL design, verification
• Full-time role on Starlink program with locations in Palo Alto, Irvine, or Redmond.
• Hands-on, self-starter candidate to design, verify, and bring-up complex ASIC/FPGA/RFIC blocks.

🎯 Requirements

• Bachelor’s, master’s, or PhD in engineering/math/physics (2026/2027 grad).
• Experience with ASIC/SOC/FPGA/RFIC/MMIC and relevant design flows.
• Proficiency in SystemVerilog/Verilog/VHDL and C/C++/Python for automation.
• Knowledge of DSP, RTL design, and physical design concepts.

🎁 Benefits

• Competitive compensation and stock options; comprehensive medical/dental/vision.
• 401(k) plan, disability insurance, parental leave, vacation, holidays, and commuter shuttles.
• ITAR compliance and equal opportunity employer; relocation and visa details subject to policy.