Design Verification Engineer

📋 Description ASIC design verification in Neuralink SoC team Focus on high-throughput, low-power DSP modules Work from architecture to RTL and verification flow 🎯 Requirements Minimum 3 years in digital ASIC verification Excellence in SystemVerilog Automation with Python, Perl, Makefile, Tcl, UNIX shell Experience with code coverage and regression setup Test benches, complex SoC verification exp 🎁 Benefits Competitive base salary + RSU equity Full benefits: medical, dental, vision Paid holidays and commuter benefits Meals provided; 401(k) (interns excluded initially) Growth opportunities and strong team