HPC SoC Timing Design Engineer/Leader
HopHRRemotely
static timing analysistiming constraint analysislogic synthesisverilog hdldigital lsi designautomotive soc
Job Description
📋 Description Design Engineer or Leader for SoC Timing Design (STA/SDC/Synthesis). Static timing analysis using STA tools. Timing constraint analysis with STA tools and in-house tools. Logic synthesis with commercial tools. Collaborate with overseas offices and design centers. 🎯 Requirements Over 5 years in digital LSI design, with 3+ years in timing design. Business-level English or Japanese; the other conversational. Understanding Verilog-HDL. Experience using English in a professional setting. Management experience. Interest in future management roles.
